Benefits:

• Competitive Salary Offering

• Company Equity Package

Benefits:

• Competitive Salary Offering

• Company Equity Package

Benefits:

• Limitless growth opportunities

• Shape your career

• Explore your passions

• Generous PTO

• Fitness benefits

Benefits:

• Limitless growth opportunities

• Shape your career

• Explore your passions

• Generous PTO

• Fitness benefits

Benefits:

• Limitless growth opportunities

• Shape your career

• Explore your passions

• Generous PTO

• Fitness benefits

Benefits:

• Limitless growth opportunities

• Shape your career

• Explore your passions

• Generous PTO

• Fitness benefits

Benefits:

• Competitive salary

• equity

• comprehensive benefits package

• Flexible work environment with remote work options

Education Requirements:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.

Experience Requirements:

• 10+ years of experience in ASIC design, with a strong focus on high-performance computing or AI accelerators.

Responsibilities:

• Lead the architecture and design of ASIC solutions for AI inference workloads.

• Define microarchitecture, develop RTL design, and drive implementation from concept to silicon.

• Work closely with verification and validation teams to ensure robust functional correctness.

• Collaborate with physical design teams to optimize for power, performance, and area (PPA).

• Define and drive design methodologies, best practices, and process improvements.

Benefits:

• Competitive salary

• equity

• comprehensive benefits package

• Flexible work environment with remote work options

Education Requirements:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.

Experience Requirements:

• 10+ years of experience in ASIC design, with a strong focus on high-performance computing or AI accelerators.

Responsibilities:

• Lead the architecture and design of ASIC solutions for AI inference workloads.

• Define microarchitecture, develop RTL design, and drive implementation from concept to silicon.

• Work closely with verification and validation teams to ensure robust functional correctness.

• Collaborate with physical design teams to optimize for power, performance, and area (PPA).

• Define and drive design methodologies, best practices, and process improvements.

Benefits:

• Competitive salary

• equity

• comprehensive benefits package

• Flexible work environment with remote work options

Education Requirements:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.

Experience Requirements:

• 10+ years of experience in ASIC design, with a strong focus on high-performance computing or AI accelerators.

Responsibilities:

• Lead the architecture and design of ASIC solutions for AI inference workloads.

• Define microarchitecture, develop RTL design, and drive implementation from concept to silicon.

• Work closely with verification and validation teams to ensure robust functional correctness.

• Collaborate with physical design teams to optimize for power, performance, and area (PPA).

• Define and drive design methodologies, best practices, and process improvements.

Benefits:

• Competitive salary

• equity

• comprehensive benefits package

• Flexible work environment with remote work options

Education Requirements:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.

Experience Requirements:

• 10+ years of experience in ASIC verification, including leadership roles.

Responsibilities:

• Develop and execute verification strategies for AI inference ASICs.

• Define and implement comprehensive test plans and verification methodologies.

• Lead the development of verification environments using SystemVerilog/CocoTB.

• Create and maintain simulation testbenches, directed and constrained-random tests.

• Collaborate with design and architecture teams to ensure functional coverage and closure.

Benefits:

• Competitive salary

• equity

• comprehensive benefits package

• Flexible work environment with remote work options

Education Requirements:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.

Experience Requirements:

• 10+ years of experience in ASIC verification, including leadership roles.

Responsibilities:

• Develop and execute verification strategies for AI inference ASICs.

• Define and implement comprehensive test plans and verification methodologies.

• Lead the development of verification environments using SystemVerilog/CocoTB.

• Create and maintain simulation testbenches, directed and constrained-random tests.

• Collaborate with design and architecture teams to ensure functional coverage and closure.

Benefits:

• Competitive salary

• equity

• comprehensive benefits package

• Flexible work environment with remote work options

Education Requirements:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.

Experience Requirements:

• 10+ years of experience in ASIC verification, including leadership roles.

Responsibilities:

• Develop and execute verification strategies for AI inference ASICs.

• Define and implement comprehensive test plans and verification methodologies.

• Lead the development of verification environments using SystemVerilog/CocoTB.

• Create and maintain simulation testbenches, directed and constrained-random tests.

• Collaborate with design and architecture teams to ensure functional coverage and closure.

Benefits:

• Competitive salary

• equity

• comprehensive benefits package

• Flexible work environment with remote work options

Education Requirements:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.

Experience Requirements:

• 10+ years of experience in ASIC verification, including leadership roles.

Responsibilities:

• Develop and execute verification strategies for AI inference ASICs.

• Define and implement comprehensive test plans and verification methodologies.

• Lead the development of verification environments using SystemVerilog/CocoTB.

• Create and maintain simulation testbenches, directed and constrained-random tests.

• Collaborate with design and architecture teams to ensure functional coverage and closure.

Education Requirements:

• BA/BS required, preferred in technical subject like Computer Science, Physics, Applied Math, or Electrical Engineering

Experience Requirements:

• Experience building performance dashboards

• Experience with novel hardware platforms

Experience Requirements:

• 10+ years of professional experience in C++ software development, with a focus on performance-critical applications.

Responsibilities:

• Design, implement, and optimize high-performance inference software for LLMs on custom hardware.

• Develop and fine-tune C++-based libraries that efficiently utilize SIMD instructions, threading, and memory hierarchy.

• Work closely with FPGA and systems engineers to design efficient data movement and computational offloading between x86 CPUs and FPGAs.

Experience Requirements:

• 10+ years of professional experience in C++ software development, with a focus on performance-critical applications.

Responsibilities:

• Design, implement, and optimize high-performance inference software for LLMs on custom hardware.

• Develop and fine-tune C++-based libraries that efficiently utilize SIMD instructions, threading, and memory hierarchy.

• Work closely with FPGA and systems engineers to design efficient data movement and computational offloading between x86 CPUs and FPGAs.

Experience Requirements:

• 7+ years of professional experience in C++ software development, with a focus on performance-critical applications.

Responsibilities:

• Design and implement high-performance inference software for LLMs on custom hardware.

• Develop and optimize C++-based libraries that efficiently utilize SIMD instructions, threading, and memory hierarchy.

• Work closely with FPGA and systems engineers to ensure efficient data movement and computational offloading between x86 CPUs and FPGAs.