Myrtle.ai

Education Requirements:

• Masters degree in Engineering, Mathematics or other Scientific Discipline

Experience Requirements:

• At least 5 years experience generating clear, well-documented, and well-tested SystemVerilog, Verilog or VHDL code

Other Requirements:

• Worked with FPGA EDA tools such as Quartus or Vivado

• Worked with software languages such as C, C++, Python

• Familiarity with Linux development environments, version control and CI systems

• Experience of bringing up full FPGA designs and debugging on hardware

• Experience optimising RTL designs to achieve timing closure

• Good verbal and written communication skills

Responsibilities:

• Writing and testing IP components in SystemVerilog for FPGA

• Building full applications for FPGA using our IP library

• Integrating with third party IP for external memory PCIe subsystems

• Extending IP verification code and integrating into automated test environments

• Working with software interface routines to support FPGA integration into the software stacks

Experience Requirements:

• At least 5 years generating clear, well-documented, and well-tested code

Other Requirements:

• Built large C++ or Rust codebases

• Experience working on high performance or real-time applications

• Worked in a multi processor – multi threaded environment.

• Worked with cloud deployed applications

• Familiarity with Linux driver-level / kernel-level programming

• Experience of coaching and developing others

Responsibilities:

• Shipping Rust applications for real time deployment of machine learning powered services

• Optimising code for the latest larger server, multicore CPUs

• Creating code to handle high throughput, timing critical services in local and cloud based data centers

• Releasing customer and open source application repositories

• Working with our ML team and ML frameworks for inference optimization

Education Requirements:

• A degree in Engineering, Computer Science or other Technical discipline

Experience Requirements:

• Experience simulating and verifying large RTL designs

• At least 5 years generating clear, well-documented, and maintainable SystemVerilog code

Other Requirements:

• Experience with C/C++ or other imperative coding language

• Good verbal and written communication skills

• Experience working in Linux based development environments

• An interest in learning about AI Inference compute architectures

Responsibilities:

• Designing SystemVerilog based verification environments to support a range of IP products

• Optimizing verification code to enable fast simulation support for software integration

• Communicating the verification environment design and supporting others to use, add and extend testing during IP development

• Learning about AI inference compute architectures and mathematical techniques

• Working alongside our ML, Software and FPGA developers