Benefits:

• 20 vacation days

• Strong health and extended health benefits

• Unlimited sick days

• Stock options

Education Requirements:

• 5+ years of experience in 7nm and smaller finFET nodes

Experience Requirements:

• 5+ years of experience in 7nm and smaller finFET nodes

Other Requirements:

• Expertise in using industry standard CAD tools such as Cadence Virtuoso

• Experience with closing LVS, DRC, ERC, SRAM, other PVERF checks on custom designs

• Understanding of EMIR and mitigations

• Linux or Unix

Responsibilities:

• Collaborate with circuit designers to understand electrical and physical needs of complex custom memory array designs

• Design custom standard cell compliant transistor level layout meeting strenuous PPA goals

• Drive learning and optimization for physical effects of process variation